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ltc2249 1 2249f features descriptio u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. sample rate: 80msps single 3v supply (2.7v to 3.4v) low power: 222mw 73db snr at 70mhz input 90db sfdr at 70mhz input no missing codes flexible input: 1v p-p to 2v p-p range 575mhz full power bandwidth s/h clock duty cycle stabilizer shutdown and nap modes pin compatible family 80msps: ltc2229 (12-bit), ltc2249 (14-bit) 65msps: ltc2228 (12-bit), ltc2248 (14-bit) 40msps: ltc2227 (12-bit), ltc2247 (14-bit) 25msps: ltc2226 (12-bit), ltc2246 (14-bit) 10msps: ltc2225 (12-bit), ltc2245 (14-bit) 32-pin (5mm 5mm) qfn package 14-bit, 80msps low power 3v adc the ltc 2249 is a 14-bit 80msps, low power 3v a/d converter designed for digitizing high frequency, wide dynamic range signals. the ltc2249 is perfect for de- manding imaging and communications applications with ac performance that includes 73db snr and 90db sfdr for signals well beyond the nyquist frequency. dc specs include 1lsb inl (typ), 0.5lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1.2lsb rms . a single 3v supply allows low power operation. a separate output supply allows the outputs to drive 0.5v to 3.3v logic. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high perfor- mance at full speed for a wide range of clock duty cycles. snr vs input frequency, ?db, 2v range applicatio s u wireless and wired broadband communication imaging systems ultrasound spectral analysis portable instrumentation + input s/h correction logic output drivers 14-bit pipelined adc core clock/duty cycle control flexible reference d13 d0 clk refh refl analog input 2229 ta01 ov dd ognd input frequency (mhz) 0 65 snr (dbfs) 66 68 69 70 75 72 50 100 2249 g09 67 73 74 71 150 200
ltc2249 2 2249f 32 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 ain + ain refh refh refl refl v dd gnd d10 d9 d8 ov dd ognd d7 d6 d5 v dd v cm sense mode of d13 d12 d11 clk shdn oe d0 d1 d2 d3 d4 33 absolute axi u rati gs w ww u package/order i for atio uu w ov dd = v dd (notes 1, 2) supply voltage (v dd ) ................................................. 4v digital output ground voltage (ognd) ....... 0.3v to 1v analog input voltage (note 3) ..... 0.3v to (v dd + 0.3v) digital input voltage .................... 0.3v to (v dd + 0.3v) digital output voltage ................ 0.3v to (ov dd + 0.3v) power dissipation ............................................ 1500mw operating temperature range ltc2249c ............................................... 0 c to 70 c ltc2249i .............................................40 c to 85 c storage temperature range ..................65 c to 125 c lead temperature (soldering, 10 sec).................. 300 c order part number qfn part* marking t jmax = 125 c, ja = 34 c/w exposed pad is gnd (pin 33) must be soldered to pcb 2249 ltc2249cuh ltc2249iuh consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) parameter conditions min typ max units resolution (no missing codes) 14 bits integral linearity error differential analog input (note 5) ? 1 4 lsb differential linearity error differential analog input ? 0.5 1 lsb offset error (note 6) ?2 212 mv gain error external reference 2.5 0.5 2.5 %fs offset drift 10 v/ c full-scale drift internal reference 30 ppm/ c external reference 15 ppm/ c transition noise sense = 1v 1 lsb rms co verter characteristics u symbol parameter conditions min typ max units v in analog input range (a in + ? in ) 2.7v < v dd < 3.4v (note 7) 1v to 2v v v in,cm analog input common mode differential input (note 7) 1 1.5 1.9 v i in analog input leakage current 0v < a in + , a in < v dd ? 1 a i sense sense input leakage 0v < sense < 1v ? 3 a i mode mode pin leakage ? 3 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms cmrr analog input common mode rejection ratio 80 db a alog i put u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4)
ltc2249 3 2249f the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = ?dbfs. (note 4) symbol parameter conditions min typ max units snr signal-to-noise ratio 5mhz input 73 db 40mhz input 70.8 73 db 70mhz input 73 db 140mhz input 72.6 db sfdr spurious free dynamic range 5mhz input 90 db 2nd or 3rd harmonic 40mhz input 75 90 db 70mhz input 90 db 140mhz input 85 db sfdr spurious free dynamic range 5mhz input 95 db 4th harmonic or higher 40mhz input 81 95 db 70mhz input 95 db 140mhz input 90 db s/(n+d) signal-to-noise plus distortion ratio 5mhz input 72.9 db 40mhz input 70.2 72.8 db 70mhz input 72.8 db 140mhz input 72.1 db i md intermodulation distortion f in1 = 28.2mhz, f in2 = 26.8mhz 90 db full power bandwidth figure 8 test circuit 575 mhz dy a ic accuracy u w parameter conditions min typ max units v cm output voltage i out = 0 1.475 1.500 1.525 v v cm output tempco 30 ppm/ c v cm line regulation 2.7v < v dd < 3.4v 3 mv/v v cm output resistance ?ma < i out < 1ma 4 ? i ter al refere ce characteristics uu u (note 4)
ltc2249 4 2249f digital i puts a d digital outputs u u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) power require e ts w u the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 8) symbol parameter conditions min typ max units v dd analog supply voltage (note 9) 2.7 3 3.4 v ov dd output supply voltage (note 9) 0.5 3 3.6 v iv dd supply current 74 86 ma p diss power dissipation 222 258 mw p shdn shutdown power shdn = h, oe = h, no clk 2 mw p nap nap mode power shdn = h, oe = l, no clk 15 mw symbol parameter conditions min typ max units logic inputs (clk, oe, shdn) v ih high level input voltage v dd = 3v 2v v il low level input voltage v dd = 3v 0.8 v i in input current v in = 0v to v dd ?0 10 a c in input capacitance (note 7) 3 pf logic outputs ov dd = 3v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = ?0 a 2.995 v i o = ?00 a 2.7 2.99 v v ol low level output voltage i o = 10 a 0.005 v i o = 1.6ma 0.09 0.4 v ov dd = 2.5v v oh high level output voltage i o = ?00 a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = ?00 a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v
ltc2249 5 2249f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3v, f sample = 80mhz, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from 0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: v dd = 3v, f sample = 80mhz, input range = 1v p-p with differential drive. note 9: recommended operating conditions. ti i g characteristics u w the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 4) symbol parameter conditions min typ max units f s sampling frequency (note 9) 1 80 mhz t l clk low time duty cycle stabilizer off 5.9 6.25 500 ns duty cycle stabilizer on (note 7) 5 6.25 500 ns t h clk high time duty cycle stabilizer off 5.9 6.25 500 ns duty cycle stabilizer on (note 7) 5 6.25 500 ns t ap sample-and-hold aperture delay 0ns t d clk to data delay c l = 5pf (note 7) 1.4 2.7 5.4 ns data access time after oe c l = 5pf (note 7) 4.3 10 ns bus relinquish time (note 7) 3.3 8.5 ns pipeline 6 cycles latency typical dnl, 2v range typical inl, 2v range 8192 point fft, f in = 5mhz, ?db, 2v range typical perfor a ce characteristics uw code 0 inl error (lsb) 0 0.5 1.0 16384 2249 g01 ?.5 ?.0 ?.0 4096 8192 12288 ?.5 2.0 1.5 code 0 dnl error (lsb) 0.2 0.4 0.6 16384 2249 g02 0 ?.2 ?.0 4096 8192 12288 ?.6 ?.4 ?.8 1.0 0.8 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 0 35 2249 g03 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?10 ?20 5 15 25 10 20 30 40
ltc2249 6 2249f typical perfor a ce characteristics uw 8192 point fft, f in = 30mhz, ?db, 2v range 8192 point fft, f in = 70mhz, ?db, 2v range 8192 point fft, f in = 140mhz, ?db, 2v range grounded input histogram snr vs input frequency, ?db, 2v range 8192 point 2-tone fft, f in = 28.2mhz and 26.8mhz, ?db, 2v range sfdr vs input frequency, ?db, 2v range snr and sfdr vs sample rate, 2v range, f in = 5mhz, ?db snr and sfdr vs clock duty cycle frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 0 35 2249 g04 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?10 ?20 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 0 35 2249 g05 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?10 ?20 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 0 35 2249 g06 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?10 ?20 5 15 25 10 20 30 40 frequency (mhz) 0 amplitude (db) ?0 ?0 ?0 0 35 2249 g07 ?0 ?00 ?0 ?0 ?0 ?0 ?0 ?10 ?20 5 15 25 10 20 30 40 code 8201 26 178 552 1987 5194 6150 35969 8203 8205 8207 8209 count 30000 40000 50000 2249 g08 20000 10000 25000 35000 45000 15000 5000 0 12558 43161 25292 input frequency (mhz) 0 65 snr (dbfs) 66 68 69 70 75 72 50 100 2249 g09 67 73 74 71 150 200 input frequency (mhz) 0 85 90 100 150 2249 g10 80 75 50 100 200 70 65 95 sfdr (dbfs) sample rate (msps) 0 snr and sfdr (dbfs) 80 90 100 80 2249 g11 70 60 50 10 20 30 40 50 60 70 90 100 110 sfdr snr clock duty cycle (%) 30 snr and sfdr (dbfs) 85 90 60 2249 g12 80 75 40 50 35 65 45 55 70 70 95 sfdr: dcs on snr: dcs on snr: dcs off sfdr: dcs off
ltc2249 7 2249f typical perfor a ce characteristics uw snr vs input level, f in = 70mhz, 2v range i ovdd vs sample rate, 5mhz sine wave input, ?db, o vdd = 1.8v i vdd vs sample rate, 5mhz sine wave input, ?db sfdr vs input level, f in = 70mhz, 2v range uu u pi fu ctio s a in + (pin 1): positive differential analog input. a in - (pin 2): negative differential analog input. refh (pins 3, 4): adc high reference. short together and bypass to pins 5, 6 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 5, 6 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. refl (pins 5, 6): adc low reference. short together and bypass to pins 3, 4 with a 0.1 f ceramic chip capacitor as close to the pin as possible. also bypass to pins 3, 4 with an additional 2.2 f ceramic chip capacitor and to ground with a 1 f ceramic chip capacitor. v dd (pins 7, 32): 3v supply. bypass to gnd with 0.1 f ceramic chip capacitors. gnd (pin 8): adc power ground. clk (pin 9): clock input. the input sample starts on the positive edge. shdn (pin 10): shutdown mode selection pin. connect- ing shdn to gnd and oe to gnd results in normal input level (dbfs) ?0 ?0 ?0 snr (dbc and dbfs) 30 40 50 ?0 0 2249 g13 20 10 0 ?0 ?0 dbfs dbc ?0 60 70 80 input level (dbfs) ?0 sfdr (dbc and dbfs) 60 dbc dbfs 90 100 0 2249 g14 50 40 0 ?0 ?0 ?0 20 120 110 80 70 30 10 100dbc sfdr reference line sample rate (msps) 0 50 i vdd (ma) 55 65 70 75 85 10 50 70 2249 g15 60 80 40 90 100 20 30 60 80 2v range 1v range sample rate (msps) 0 0 i ovdd (ma) 1 3 4 5 7 10 50 70 2249 g16 2 6 40 90 100 20 30 60 80
ltc2249 8 2249f operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin 11): output enable pin. refer to shdn pin function. d0 ?d13 (pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): digital outputs. d13 is the msb. ognd (pin 20): output driver ground. ov dd (pin 21): positive supply for the output drivers. bypass to ground with 0.1 f ceramic chip capacitor. of (pin 28): over/under flow output. high when an over or under flow has occurred. mode (pin 29): output format and clock duty cycle stabilizer selection pin. connecting mode to gnd selects straight binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2? complement output format and turns the clock duty cycle stabilizer on. v dd selects 2? complement output format and turns the clock duty cycle stabilizer off. sense (pin 30): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 31): 1.5v output and input common mode bias. bypass to ground with 2.2 f ceramic chip capacitor. gnd (exposed pad) (pin 33): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. uu u pi fu ctio s fu n ctio n al block diagra uu w shift register and correction diff ref amp ref buf 2.2 f 1 f1 f 0.1 f internal clock signals refh refl clock/duty cycle control range select 1.5v reference first pipelined adc stage fifth pipelined adc stage sixth pipelined adc stage fourth pipelined adc stage second pipelined adc stage refh refl clk oe mode ognd ov dd 2249 f01 input s/h sense v cm a in a in + 2.2 f third pipelined adc stage output drivers control logic shdn of d13 d0 figure 1. functional block diagram
ltc2249 9 2249f ti i g diagra u ww dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log (v2 2 + v3 2 + v4 2 + . . . vn 2 )/v1 where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. applicatio s i for atio wu uu intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at the sum and differ- ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa ?fb and 2fb ?fa. the intermodulation distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. input bandwidth the input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n ?5 n ?4 n ?3 n ?2 clk d0-d13, of 2249 td01 n ?6 n ?1
ltc2249 10 2249f aperture delay time the time from when clk reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = ?0log (2 ) ?f in ?t jitter converter operation as shown in figure 1, the ltc2249 is a cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value six cycles later (see the timing diagram section). for optimal ac performance the analog inputs should be driven differentially. for cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. the clk input is single-ended. the ltc2249 has two phases of operation, determined by the state of the clk input pin. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when clk is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the ?nput s/h?shown in the block diagram. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2249 cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capaci- tance associated with each input. figure 2. equivalent input circuit v dd v dd v dd 15 ? 15 ? c parasitic 1pf c parasitic 1pf c sample 4pf c sample 4pf ltc2249 a in + a in clk 2249 f02 during the sample phase when clk is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. when clk transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when clk is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as clk transitions from applicatio s i for atio wu uu
ltc2249 11 2249f applicatio s i for atio wu u u high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. single-ended input for cost sensitive applications, the analog inputs can be driven single-ended. with a single-ended input the har- monic distortion and inl will degrade, but the snr and dnl will remain unchanged. for a single-ended input, a in + should be driven with the input signal and a in should be connected to 1.5v or v cm . common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.5v. the v cm output pin (pin 31) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2 f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dynamic performance of the ltc2249 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and reactance can influence sfdr. at the falling edge of clk, the sample- and-hold circuit will connect the 4pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when clk rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 ? or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2249 being driven by an rf transformer with a center tapped secondary. the second- ary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the trans- former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 ? for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain band- width of most op amps will limit the sfdr at high input frequencies. figure 3. single-ended to differential conversion using a transformer 25 ? 25 ? 25 ? 25 ? 0.1 f a in + a in 12pf 2.2 f v cm ltc2249 analog input 0.1 ft1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 2249 f03 figure 4. differential drive with an amplifier 25 ? 25 ? 12pf 2.2 f v cm ltc2249 2249 f04 + + cm analog input high speed differential amplifier a in + a in
ltc2249 12 2249f figure 5 shows a single-ended input circuit. the imped- ance seen by the analog inputs should be matched. this circuit is not recommended if low distortion is required. applicatio s i for atio wu uu reference operation figure 9 shows the ltc2249 reference circuitry consisting of a 1.5v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage refer- ence can be configured for two pin selectable input ranges of 2v ( 1v differential) or 1v ( 0.5v differential). tying the sense pin to v dd selects the 2v range; tying the sense pin to v cm selects the 1v range. the 1.5v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener- ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.5v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifier generates the high and low refer- ence for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has two pins. the multiple output pins are needed to reduce package inductance. bypass capacitors must be connected as shown in figure 9. other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1 f ceramic capacitor. figure 5. single-ended drive 25 ? 0.1 f analog input v cm a in + a in 10k 12pf 2249 f05 2.2 f 10k 25 ? 0.1 f ltc2249 the 25 ? resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequencies above 70mhz, the input circuits of figure 6, 7 and 8 are recommended. the balun trans- former gives better high frequency response than a flux coupled center tapped transformer. the coupling capaci- tors allow the analog inputs to be dc biased at 1.5v. in figure 8, the series inductors are impedance matching elements that maximize the adc bandwidth. figure 6. recommended front end circuit for input frequencies between 70mhz and 170mhz 25 ? 25 ? 12 ? 12 ? 0.1 f a in + a in 8pf 2.2 f v cm ltc2249 analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 2249 f06 figure 8. recommended front end circuit for input frequencies above 300mhz 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm ltc2249 analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors are 0402 package size 2249 f07 25 ? 25 ? 0.1 f a in + a in 2.2 f v cm ltc2249 analog input 0.1 f 0.1 f t1 t1 = ma/com, etc 1-1-13 resistors, capacitors, inductors are 0402 package size 2249 f08 6.8nh 6.8nh figure 7. recommended front end circuit for input frequencies between 170mhz and 300mhz
ltc2249 13 2249f applicatio s i for atio wu uu the noise performance of the ltc2249 can depend on the clock signal quality as much as on the analog input. any noise present on the clock signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digitiz- ing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, filter the clk signal to reduce wideband noise and distortion products generated by the source. maximum and minimum conversion rates the maximum conversion rate for the ltc2249 is 80msps. for the adc to operate properly, the clk signal should have a 50% ( 5%) duty cycle. each half cycle must have at least 5.9ns for the adc internal circuitry to have enough settling time for proper operation. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise perfor- mance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 5.7db. see the typical performance charac- teristics section. driving the clock input the clk input can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low-jitter squaring circuit before the clk pin (see figure 11). v cm refh sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ?v sense for 0.5v < v sense < 1v 1.5v refl 2.2 f 2.2 f internal adc high reference buffer 0.1 f 2249 f09 ltc2249 4 ? diff amp 1 f 1 f internal adc low reference 1.5v bandgap reference 1v 0.5v range detect and control figure 9. equivalent reference circuit v cm sense 1.5v 0.75v 2.2 f 12k 1 f 12k 2249 f10 ltc2249 figure 10. 1.5v range adc clk 50 ? 0.1 f 0.1 f 4.7 f 1k 1k ferrite bead clean supply sinusoidal clock input 2249 f11 nc7svu04 ltc2249 figure 11. sinusoidal single-ended clk drive
ltc2249 14 2249f the lower limit of the ltc2249 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating fre- quency for the ltc2249 is 1msps. digital outputs digital output buffers figure 12 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 ? to external circuitry and may eliminate the need for external damping resistors. as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltc2249 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. data format using the mode pin, the ltc2249 parallel digital output can be selected for offset binary or 2? complement format. connecting mode to gnd or 1/3v dd selects straight binary output format. connecting mode to 2/3v dd or v dd selects 2? complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 1 shows the logic states for the mode pin. figure 12. digital output buffer ltc2249 2249 f12 ov dd v dd v dd 0.1 f 43 ? typical data output ognd ov dd 0.5v to v dd predriver logic data from latch oe table 1. mode pin function clock duty mode pin output format cycle stablizer 0 straight binary off 1/3v dd straight binary on 2/3v dd 2? complement on v dd 2? complement off overflow bit when of outputs a logic high the converter is either overranged or underranged. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to the v dd of the part. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of. the data ac- cess and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed op- eration. the output hi-z state is intended for use during long periods of inactivity. applicatio s i for atio wu uu
ltc2249 15 2249f applicatio s i for atio wu uu sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dissipates 15mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. grounding and bypassing the ltc2249 requires a printed circuit board with a clean, unbroken ground plane. a multilayer board with an inter- nal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refh, and refl pins. bypass capaci- tors must be located as close to the pins as possible. of particular importance is the 0.1 f capacitor between refh and refl. this capacitor should be placed as close to the device as possible (1.5mm or less). a size 0402 ceramic capacitor is recommended. the large 2.2 f ca- pacitor between refh and refl can be somewhat further away. the traces connecting the pins and bypass capaci- tors must be kept short and should be made as wide as possible. the ltc2249 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2249 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area.
ltc2249 16 2249f applicatio s i for atio wu uu 1 2 c8 0.1 f c11 0.1 f 3 4 5 v dd 7 v dd v dd gnd 9 32 v cm 31 30 29 33 jp2 oe 10 11 8 c7 2.2 f c6 1 f c9 1 f c4 0.1 f c2 8.2pf v dd v dd v dd gnd jp1 shdn c15 2.2 f c16 0.1 f c18 0.1 f c25 4.7 f e2 v dd 3v e4 pwr gnd v dd v cc 2249 ta02 c17 0.1 f c20 0.1 f c19 0.1 f c14 0.1 f r10 33 ? e1 ext ref r14 1k r15 1k r16 1k r7 1k r8 49.9 ? r3 24.9 ? r2 12.4 ? r6 12.4 ? r1 opt r4 24.9 ? r5 1k t1 etc1-1-13 c1 0.1 f c3 0.1 f j3 clock input nc7svu04 nc7svu04 c13 0.1 f c10 0.1 f c5 4.7 f 6.3v l1 bead v dd c12 0.1 f r9 1k j1 analog input a in + a in refh refh 6 refl refl v dd clk shdn v dd v cm sense mode gnd ltc2249 oe d12 d11 gnd d0 d1 d2 d3 d5 d4 d6 d8 d9 d13 of ov dd v cc ognd d10 d7 26 25 12 13 14 15 17 16 18 22 23 27 28 21 20 24 19 oe1 i 0 oe2 le1 le2 v cc v cc v cc gnd gnd gnd i 1 i 2 i 4 i 3 i 5 i 7 i 8 i 12 i 11 i 10 i 13 i 14 i 15 i 9 o11 o10 i 6 v cc o0 gnd gnd gnd v cc v cc gnd 34 45 39 42 25 48 24 1 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 v cc 28 74vcx16373mtd 31 21 15 18 10 4 7 r n1c 33 ? 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 gnd o1 o2 o4 o3 o5 o7 o8 o12 o13 o14 o15 o9 o6 25 23 27 29 31 33 35 37 39 21 19 15 17 13 9 7 1 3 5 2 4 11 26 24 30 28 34 32 38 40 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 3201s-40g1 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 36 a3 a2 a1 a0 sda wp v cc 1 2 3 4 8 24lc025 7 6 5 scl 22 20 16 18 14 10 8 6 12 1 2 3 5 4 v cm 12 v dd v dd 34 2/3v dd 56 1/3v dd 78 gnd jp4 mode 12 v dd 34 v cm v dd v cm 56 ext ref jp3 sense r n1b 33 ? r n1a 33 ? r n2d 33 ? r n2c 33 ? r n2b 33 ? r n2a 33 ? r n3d 33 ? r n3c 33 ? r n3b 33 ? r n3a 33 ? r n4d 33 ? r n4b 33 ? r n4a 33 ? r13 10k r11 10k r12 10k r n4c 33 ? r n1d 33 ? c28 1 f c27 0.01 f v cc v dd nc7sv86p5x byp gnd adj out shdn gnd in 1 2 3 4 8 lt1763 7 6 5 gnd r18 100k r17 105k c26 10 f 6.3v e3 gnd c21 0.1 f c22 0.1 f c23 0.1 f c24 0.1 f
ltc2249 17 2249f applicatio s i for atio wu uu silkscreen top topside inner layer 2 gnd
ltc2249 18 2249f applicatio s i for atio wu uu inner layer 3 power bottomside silkscreen bottom
ltc2249 19 2249f uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) package descriptio u 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (note 6) 0.40 0.10 0.23 typ (4 sides) 31 1 2 32 bottom view?xposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0603 0.50 bsc 0.200 ref 0.00 ?0.05 0.70 0.05 3.45 0.05 (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc2249 20 2249f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt/tp 1004 1k ?printed in usa related parts part number description comments ltc1741 12-bit, 65msps adc 72db snr, 87db sfdr, 48-pin tssop package LTC1742 14-bit, 65msps adc 76.5db snr, 90db sfdr, 48-pin tssop package ltc1743 12-bit, 50msps adc 72.5db snr, 90db sfdr, 48-pin tssop package ltc1744 14-bit, 50msps adc 77db snr, 90db sfdr, 48-pin tssop package ltc1745 12-bit, 25msps adc 72.2db snr, 380mw sfdr, 48-pin tssop package ltc1746 14-bit, 25msps adc 77.5db snr, 390mw sfdr, 48-pin tssop package ltc1747 12-bit, 80msps adc 72db snr, 87db sfdr, 48-pin tssop package ltc1748 14-bit, 80msps adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1749 12-bit, 80msps wideband adc up to 500mhz if undersampling, 87db sfdr ltc1750 14-bit, 80msps wideband adc up to 500mhz if undersampling, 90db sfdr ltc2220 12-bit, 170msps adc 890mw, 67.7db snr, 9mm x 9mm qfn package ltc2221 12-bit, 135msps adc 630mw, 67.8db snr, 9mm x 9mm qfn package ltc2222 12-bit, 105msps adc 475mw, 68.4db snr, 7mm x 7mm qfn package ltc2223 12-bit, 80msps adc 366mw, 68.5db snr, 7mm x 7mm qfn package ltc2224 12-bit, 135msps adc 630mw, 67.6db snr, 7mm x 7mm qfn package ltc2225 12-bit, 10msps adc 60mw, 71.3db snr, 5mm x 5mm qfn package ltc2226 12-bit, 25msps adc 75mw, 71.4db snr, 5mm x 5mm qfn package ltc2227 12-bit, 40msps adc 120mw, 71.4db snr, 5mm x 5mm qfn package ltc2228 12-bit, 65msps adc 205mw, 71.3db snr, 5mm x 5mm qfn package ltc2229 12-bit, 80msps adc 211mw, 70.6db snr, 5mm x 5mm qfn package ltc2230 10-bit, 170msps adc 890mw, 61.2db snr, 9mm x 9mm qfn package ltc2231 10-bit, 135msps adc 630mw, 61.2db snr, 9mm x 9mm qfn package ltc2232 10-bit, 105msps adc 475mw, 61.3db snr, 7mm x 7mm qfn package ltc2233 10-bit, 80msps adc 366mw, 61.3db snr, 7mm x 7mm qfn package ltc2234 10-bit, 135msps adc 630mw, 61.2db snr, 7mm x 7mm qfn package ltc2236 10-bit, 25msps adc 75mw, 61.8db snr, 5mm 5mm qfn package ltc2237 10-bit, 40msps adc 120mw, 61.8db snr, 5mm 5mm qfn package ltc2238 10-bit, 65msps adc 205mw, 61.8db snr, 5mm 5mm qfn package ltc2239 10-bit, 80msps adc 211mw, 61.6db snr, 5mm 5mm qfn package ltc2245 14-bit, 10msps adc 60mw, 74.4db snr, 5mm 5mm qfn package ltc2246 14-bit, 25msps adc 75mw, 74.5db snr, 5mm 5mm qfn package ltc2247 14-bit, 40msps adc 120mw, 74.4db snr, 5mm 5mm qfn package ltc2248 14-bit, 65msps adc 205mw, 74.3db snr, 5mm 5mm qfn package lt5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifier/adc driver 450mhz 1db bw, 47db oip3, digital gain control with digitally controlled gain 10.5db to 33ddb in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator 20dbm iip3, integrated lo quadrature generator lt5516 0.8ghz to 1.5ghz direct conversion quadrature demodulator 21.5dbm iip3, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator 21dbm iip3, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 ? single-ended rf and lo ports

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